1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to a trench-capacitor vertical dynamic random access memory (DRAM) cell array in which floating-body effects have been substantially minimized. Moreover, the present invention provides a trench-capacitor vertical DRAM cell array having a compact cell structure wherein device-to-device interactions in the array regions have been reduced.
2. Background of the Invention
As conventional vertical DRAM cells are scaled below a design groundrule of about 110 nm, encroachment of the buried-strap region upon the sidewall of the adjacent storage trench cuts-off the path of holes flowing into and out of the portion of the P-well above the buried-strap region causing the device to exhibit a floating-body (i.e., well) effect.
Simulation has demonstrated that floating-well effects limit the scalability of prior art vertical DRAM arrays to a minimum distance of about 90 nm between adjacent storage trenches. A number of dynamic leakage mechanisms limiting the scalability of conventional vertical DRAM cells have been identified and quantified. Included in the dynamic leakage mechanisms are: (1) Floating-well bitline disturb (FWBD), (2) Transient drain induced barrier lowering (TDIBL), and (3) Adjacent wordline induced punchthrough (AWIPT).
The onset of serious charge loss due to each mechanism occurs at approximately 90 nm end of process deep trench (DT) to deep trench (DT) spacing. Thus, scalability of conventional vertical DRAM cells below a characteristic lithographic feature size xe2x80x9cFxe2x80x9d of 110 nm is expected to be limited by floating-well effects.
For aggressively scaled vertical metal oxide semiconductor field effect transistors (MOSFETs) in prior art vertical DRAM cells, the depletion region from the storage node diffusion (i.e., buried-strap outdiffusion) encroaches upon the sidewall of the adjacent storage trench, which results in dynamic charge loss from the storage capacitor as the bitline of an unselected device is cycled. This charge loss mechanism is identical to that published in xe2x80x9cFloating-Body Concerns for SOI Dynamic Random Access Memory (DRAM)xe2x80x9d, Proceedings, 1996 IEEE International SOI Conference, Jack Mandelman, et al. pp. 1367-137, October 1996.
Conventional vertical DRAM cells, such as disclosed in U.S. Pat. No. 5,177,576 to Kimura, et al. and U.S. Pat. No. 6,144,054 to Agahi, et al., are problematic since they do not (i) provide for a compact sub-8F2 area cell; (ii) prevent the interaction between adjacent storage cells and transistors; and (iii) prevent full depletion of majority carries from the metal oxide semiconductor field effect transistor (MOSFET) substrate and hence prevent floating body effects.
In view of the drawbacks mentioned hereinabove with conventional vertical DRAM cells, there is a continued need for developing a new and improved memory cell array which address items (i)-(iii) mentioned hereinabove.
One object of the present invention is to provide a vertical DRAM cell array that substantially eliminates floating-well effects that are typically present in conventional vertical memory cell arrays.
Another object of the present invention is to provide a vertical DRAM cell array in which device-to-device interactions in the array have been substantially reduced.
A further object of the present invention is to provide a vertical DRAM cell array that has a compact cell structure that enables the fabrication of a sub-8F2 area cell.
A further object of the present invention is to provide a vertical DRAM cell array which substantially prevents full depletion of majority carriers from the MOSFET substrate and hence substantially prevents floating-body effects.
These and other objects and advantages are achieved in the present invention by providing a DRAM cell array having the substrate body active areas formed as annular rings using the deep trench (DT) capacitor pattern. The active area annular rings, which are formed self-aligned to the DT pattern, provide dielectric isolation between adjacent cells to prevent interaction between bodies and the source/drain capacitor diffusions. Moreover, in the inventive DRAM cell array, a body contact is provided along one-side of the active area annulus opposite a single-sided buried-strap contact. The inventive body contact is comprised of a region in the silicon active area annulus where there is no formation of the buried-strap outdiffusion, and hence a direct electrical connection between the array well and the device body is provided.
One aspect of the present invention thus relates to a DRAM cell array which comprises:
a plurality of annular memory cells which are arranged in rows and columns, each annular memory cell including a vertical MOSFET and an underlying capacitor that are in electrical contact to each other through a buried-strap outdiffusion region which is present within a portion of a wall of each annular memory cell such that said portion partially encircles the wall, the remaining portions of said wall of each annular memory cell have a body contact region which serves to electrically connect said annular memory cell to an adjacent array well region;
a plurality of wordlines overlaying said vertical MOSFETs, said plurality of wordlines being arranged in said row direction; and
a plurality of bitlines that are orthogonal to said plurality of wordlines.
In one embodiment of the present invention, buried-strap outdiffusion regions of adjacent annular memory cells that are arranged in the column direction are facing each other. In another embodiment of the present invention, the buried-strap outdiffusion regions of adjacent annular memory cells that are arranged in the column direction are not facing each other. In yet another embodiment of the present invention, a staggered arrangement is provided. In the staggered arrangement, buried-strap outdiffusion regions of adjacent annular memory cells in the column direction are facing each other, whereas the neighboring pair of annular memory cells in the row direction have buried-strap outdiffusion regions that are not facing each other.
The present invention also provides a method of forming the above-mentioned vertical DRAM cell array. Specifically, the method of the present invention comprises the steps of:
(a) forming a plurality of deep trenches in an array portion of a Si-containing substrate having at least a hard mask formed thereon, said plurality of deep trenches being arranged in rows and columns and including at least collar oxide regions formed on walls thereof and a recessed deep trench conductor formed between said collar oxide regions;
(b) forming a buried-strap outdiffusion region within a portion of said wall such that said portion partially encircles said wall;
(c) forming vertical MOSFETs in said plurality of deep trenches above said recessed deep trench conductor, each MOSFET having an insulating capping layer formed thereon;
(d) removing said hard mask abutting said plurality of deep trenches so as to expose sidewall portions of said MOSFETs, and forming diffusion regions in said Si-containing substrate;
(e) forming sidewall masking layers on said diffusion regions so as to cover exposed sidewall portions of said MOSFETs;
(f) etching through exposed diffusion regions and a portion of said Si-containing substrate not protected by said insulating capping layer and said sidewall masking layers so as to electrically isolate adjacent buried-strap outdiffusion regions from each other and to form annular active areas adjacent to said plurality of deep trenches;
(g) forming a mandrel material in said etched areas as well as over said insulating cap layer;
(h) forming wordlines which overlay said MOSFETs in said row direction;
(i) removing a portion of said mandrel material between adjacent deep trenches and forming bitline contacts in place thereof; and
(j) forming bitlines over said wordlines, wherein said bitlines are orthogonal to said wordlines.
In an alternative embodiment of the present invention, the hard mask is subjected to an isotropic etching process prior to forming the insulating capping layer over the MOSFETs so as to form a wide gate overhang region in the structure.